Zen 5

CPUID codeFamily 1AhCacheL1 cache80 KB (per core):
L2 cache1 MB (per core)L3 cache32 MB (per ccd)Architecture and classificationTechnology nodeTSMC N4X
TSMC N3Instruction setAMD64 (x86-64)Physical specificationsSocketsProducts, models, variantsProduct code namesBrand namesHistoryPredecessorZen 4

Zen 5 is the codename for an upcoming CPU microarchitecture by AMD, shown on their roadmap in May 2022,^[4] destined for a release in July 2024.^[5] It is the successor to Zen 4 and is fabricated on TSMC's N4X and N3E processes.^[6][7]

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server processors (codenamed "Turin"),^[8] and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").^[9]

Background

A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3nm and 4nm variants in 2024.^[10] The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".

During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".^[11]

Architecture

Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating point throughput and more accurate branch prediction.^[12]

Fabrication process

Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%.^[13][14] Additionally, Apple, as TSMC's largest customer, is given priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue.^[15] After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs.^[16]

Zen 5's CCDs are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications over significantly increased transistor density. Zen 4-based mobile processors were fabricated on the N4P node which is targeted more towards power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage.^[17] Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.^[18] Zen 5c CCDs for Turin Dense server processors are fabricated on TSMC's N3E node.

Cache and instructions

The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating point unit pipes has also been doubled. Zen 5 contains 6 Arithmetic Logic Units (ALUs), up from 4 ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.^[19]

Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating point pipe width to 512-bit. Additionally, there is greater bfloat16 throughput which is beneficial for AI workloads.

Other improvements

Other features and improvements, compared to Zen 4, include:

• A ~16% IPC uplift on average, claimed by AMD.^[20]
• Memory speeds up to DDR5-5600 and LPDDR5X-7500 are officially supported.^[21]
• Infinity Fabric clock (FCLK) has been increased to 2400 MHz.^[22]

Products

Desktop

Granite Ridge

AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors will feature between 6 and 16 cores.^[20] Ryzen 9000 processors will be released in July.

Common features of Ryzen 9000 desktop CPUs:

• Socket: AM5.
• All the CPUs support DDR5-5600 in dual-channel mode.
• All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated RDNA2 GPU with 2 CUs and base, boost clock speeds of 0.4 GHz, 2.2 GHz.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC N4 FinFET (N6 FinFET for the I/O die)^[23].

Branding and Model		Cores (threads)	Clock rate (GHz)		L3 cache (total)	TDP	Chiplets	Core config[i]	Release date	Launch price[a]
			Base	Boost
Ryzen 9	9950X[24]	16 (32)	4.3	5.7	64 MB	170 W	2 × CCD 1 × I/OD	2 × 8	July 31, 2024[25]	TBD
	9900X[24]	12 (24)	4.4	5.6		120 W		2 × 6		TBD
Ryzen 7	9700X[24]	8 (16)	3.8	5.5	32 MB	65 W	1 × CCD 1 × I/OD	1 × 8		TBD
Ryzen 5	9600X[24]	6 (12)	3.9	5.4				1 × 6		TBD

Mobile

Strix Point

The Ryzen AI 300 series of high-performance ultrathin notebook processors were announced on June 3, 2024. Codenamed Strix Point, these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point will feature a 3rd gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top end models will have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous generation Ryzen ultrathin mobile processors.^[26] Notebooks featuring Ryzen AI 300 series processors will be released in July.

Common features of Ryzen AI 300 notebook APUs:

• Socket: FP8.
• All the CPUs support DDR5-5600 or LPDDR5X-7500 in dual-channel mode.
• All the CPUs support 16 PCIe 4.0 lanes.
• Includes integrated RDNA 3.5 GPU.
• Includes XDNA 2 AI Engine (Ryzen AI).
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC 4 nm FinFET.

Branding and Model		CPU					GPU		NPU	TDP	Release date
		Cores (threads)	Clock (GHz)		L3 cache (total)	Core config[a]	Model	Clock (GHz)
			Base	Boost
Ryzen AI 9	HX 370[27]	12 (24)	2.0	5.1	24 MB	4 + 8	890M 16 CUs	2.9	Ryzen AI Up to 50 TOPS	15–54 W	July 2024
	365[27]	10 (20)		5.0		4 + 6	880M 12 CUs

Server

Turin

Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.^[28]

Turin Dense

A variant of Epyc 9005 using Zen 5c cores was also shown off at Computex. It will feature a maximum of 192 cores and 384 threads, and be manufactured on a 3 nm process.^[28]

Zen 5c

Zen 5c is a compact variant of the Zen 5 core, primarily targeted at hyperscale cloud compute server customers.^[29] It will succeed the Zen 4c core.

References